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A Verilog HDL digital architecture for delay calculation
(Planta Piloto de Ingeniería Química, 2007-02)
A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a ...
Performance evaluation of Tunnel-FET basic amplifier circuits
(Ieee, 2019-01-01)
This work analyzes the performance of measured Tunneling Field-Effect Transistors (TFET) when applied to analog circuits. The method uses a look-up table based behavioral model, taking the experimental results from a ...
Performance evaluation of Tunnel-FET basic amplifier circuits
(2019-03-14)
This work analyzes the performance of measured Tunneling Field-Effect Transistors (TFET) when applied to analog circuits. The method uses a look-up table based behavioral model, taking the experimental results from a ...
A tunnel-FET device model based on Verilog-A applied to circuit simulation
(2018-10-26)
This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental ...
A Tunnel-FET device model based on Verilog-A applied to circuit simulation
(Ieee, 2018-01-01)
This work proposes a simple methodology for using Tunnel-FET devices, which do not have any accurate first order analytic models, for allowing the integrated circuit simulation with these devices. The method uses experimental ...
Diseño de recuperador de datos y reloj adaptivo a jitter
(ITESO, 2018-08)