info:eu-repo/semantics/article
A Verilog HDL digital architecture for delay calculation
Fecha
2007-02Registro en:
Chacón-Rodríguez, A.; Martín-Pirchio, F. N.; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; A Verilog HDL digital architecture for delay calculation; Planta Piloto de Ingeniería Química; Latin American Applied Research; 37; 1; 2-2007; 41-45
0327-0793
1851-8796
CONICET Digital
CONICET
Autor
Chacón-Rodríguez, A.
Martín-Pirchio, F. N.
Julian, Pedro Marcelo
Mandolesi, Pablo Sergio
Resumen
A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations.