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Application of UTBB (SOI)-S-BE Tunnel-FET as a Dual-Technology Transistor
(Ieee, 2019-01-01)
In this work we propose for the first time the use of the recently introduced UTBB (SOI)-S-BE TFET (Ultra-Thin Body and Box Back Enhanced Silicon-On-Insulator Tunnel-FET) operating as a MOSFET device only by changing its ...
Application of UTBBBE SOI tunnel-FET as a dual-technology transistor
(2019-08-01)
In this work we propose for the first time the use of the recently introduced UTBBBE SOI TFET (Ultra-Thin Body and Box Back Enhanced Silicon-On-Insulator Tunnel-FET) operating as a MOSFET device only by changing its bias ...
Study of the utbbbe soi tunnel-fet working as a dual-technology transistor
(2021-08-23)
— In this work we further investigate the operation of theBESOI (Back-Enhanced Silicon-On Insulator) Dual-Technology FET, analyzing not only its behavior as a p-type Tunnel-FET when a negative back bias is applied to the ...
Proposal of a p-type Back-Enhanced Tunnel Field Effect Transistor
(Ieee, 2019-01-01)
In this paper we propose a new p-type Tunnel Field Effect Transistor based on the planar Back-Enhanced structure (BE-pTFET), by removing the p-type drain doping and using a back bias to obtain similar on-state behaviors ...
Proposal of a p-type Back-Enhanced Tunnel Field Effect Transistor
(2019-04-01)
In this paper we propose a new p-type Tunnel Field Effect Transistor based on the planar Back-Enhanced structure (BE-pTFET), by removing the p-type drain doping and using a back bias to obtain similar on-state behaviors ...
A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator
(IEEE, 2002)
The design of a sensing channel for implantable cardiac pacemakers in CMOS on silicon-on-insulator (SOI) technology is presented. The total current consumption is lowered to only 110nA thanks to the optimization at the ...
Novel Bending Loss Reduction Technique For The Tm Mode In Soi-based Waveguides
(IEEE-Inst Electrical Electronics Engineers IncPiscataway, 2016)
Novel Bending Loss Reduction Technique For The Tm Mode In Soi-based Waveguides
(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCPISCATAWAY, 2016)
Optimization of the Dual-Technology Back-Enhanced Field Effect Transistor
(2020-09-01)
In this paper we optimize the Dual-Technology Back-Enhanced SOI (DT BESOI) FETs varying the thickness of gate oxide, silicon film and buried oxide focusing on transfer characteristics. The DT BESOI optimization takes into ...