An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography

MIGUEL MORALES SANDOVAL; CLAUDIA FEREGRINO URIBE; RENE ARMANDO CUMPLIDO PARRA; IGNACIO ALGREDO BADILLO

info:eu-repo/semantics/article

Registro en:

http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1178

https://repositorioslatinoamericanos.uchile.cl/handle/2250/7806376

Autor

MIGUEL MORALES SANDOVAL

CLAUDIA FEREGRINO URIBE

RENE ARMANDO CUMPLIDO PARRA

IGNACIO ALGREDO BADILLO

Institución

Instituto Nacional de Astrofísica, Óptica y Electrónica (México)

Resumen

A hardware architecture for GF(2m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.

Materias

info:eu-repo/classification/cti/1

info:eu-repo/classification/cti/12

info:eu-repo/classification/cti/1203

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