| dc.creator | MIGUEL MORALES SANDOVAL | |
| dc.creator | CLAUDIA FEREGRINO URIBE | |
| dc.creator | RENE ARMANDO CUMPLIDO PARRA | |
| dc.creator | IGNACIO ALGREDO BADILLO | |
| dc.date | 2009 | |
| dc.date.accessioned | 2023-07-25T16:23:08Z | |
| dc.date.available | 2023-07-25T16:23:08Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1178 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7806376 | |
| dc.description | A hardware architecture for GF(2m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Elsevier Ltd | |
| dc.relation | citation:Morales-Sandoval, M., et al., (2009). An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography, Computers and Electrical Engineering (35): 54–58 | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/12 | |
| dc.subject | info:eu-repo/classification/cti/1203 | |
| dc.subject | info:eu-repo/classification/cti/1203 | |
| dc.title | An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography | |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/publishedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
