We report the effect of relatively high-voltage stressing (under substrate injection) on the stress-induced leakage current (SILC) and breakdown of W–La2O3 stacked structures. It is shown that the gate area of the metal–insulator–semiconductor (MIS) devices under evaluation influences their final degradation characteristics after stress. Once the samples reach breakdown, their post-breakdown current–voltage (I–V) characteristics suggest that leakage spots are highly localized and are caused by the accumulation of defects.