Interconnection opens have become important defects in nanometer technologies. The behavior of these defects depends on the structure of the affected devices, the trapped gate charge and the surrounding circuitry. This work proposes an enhanced test generation methodology to improve the detectability of interconnection opens. This test methodology is called OPVEG. OPVEG uses layout information and a commercial stuck-at ATPG. Those signal values at the coupled lines which favor the detection of the opens, under a boolean based test, are attempted to be generated. The methodology is applied to four ISCAS85 benchmark circuits. The results show that a significant number of considered coupled signals are set to proper logic values. Hence, the likelihood of detection of interconnection opens is increased. The results are also given in terms of the amount of coupling capacitance having logic conditions favoring the defect detection. This shows the OPVEG benefits. Furthermore, those lines difficult to test can be identified. This information can be used by the designer to take design for test measures.