dc.creatorRoberto Gómez
dc.creatorALEXANDRO GIRON ALLENDE
dc.creatorVICTOR HUGO CHAMPAC VILELA
dc.date2008
dc.date.accessioned2023-07-25T16:22:53Z
dc.date.available2023-07-25T16:22:53Z
dc.identifierhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1079
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7806256
dc.descriptionInterconnection opens have become important defects in nanometer technologies. The behavior of these defects depends on the structure of the affected devices, the trapped gate charge and the surrounding circuitry. This work proposes an enhanced test generation methodology to improve the detectability of interconnection opens. This test methodology is called OPVEG. OPVEG uses layout information and a commercial stuck-at ATPG. Those signal values at the coupled lines which favor the detection of the opens, under a boolean based test, are attempted to be generated. The methodology is applied to four ISCAS85 benchmark circuits. The results show that a significant number of considered coupled signals are set to proper logic values. Hence, the likelihood of detection of interconnection opens is increased. The results are also given in terms of the amount of coupling capacitance having logic conditions favoring the defect detection. This shows the OPVEG benefits. Furthermore, those lines difficult to test can be identified. This information can be used by the designer to take design for test measures.
dc.formatapplication/pdf
dc.languageeng
dc.publisherSpringer Science + Business Media
dc.relationcitation:Gómez, R., et al., (2008). A test generation methodology for interconnection opens considering signals at the coupled lines, J Electron Test (24):529–538
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Interconnection opens/Interconnection opens
dc.subjectinfo:eu-repo/classification/Coupling capacitances/Coupling capacitances
dc.subjectinfo:eu-repo/classification/Boolean testing/Boolean testing
dc.subjectinfo:eu-repo/classification/Favorable logic conditions/Favorable logic conditions
dc.subjectinfo:eu-repo/classification/Test generation methodology/Test generation methodology
dc.subjectinfo:eu-repo/classification/cti/1
dc.subjectinfo:eu-repo/classification/cti/22
dc.subjectinfo:eu-repo/classification/cti/2203
dc.subjectinfo:eu-repo/classification/cti/2203
dc.titleA test generation methodology for interconnection opens considering signals at the coupled lines
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/publishedVersion
dc.audiencestudents
dc.audienceresearchers
dc.audiencegeneralPublic


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