This work proposes a multiphase clock generator based on a ring oscillator and a delay control of every individual phase. With this individual control, correction of static errors caused by mismatch and capacitive unbalance is possible. In this document, the selection of the architecture and the different functional blocks is reported. In the case of the oscillator, a delay cell with dual tuning method is used; coarse tuning is used for frequency variation and fine tuning is used for the control of each phase. Moreover, in order to detect small delays between two signals, a delay detector based on the discharge of a capacitor, controlled by a pulse whose width is dependent on the delay to be sensed. The designed delay detector can sense delays in the order of 40 ps, with a gain of −1/20 V/ps. In the case of the oscillator, a frequency range that spans from 1.7 up to 2.25 GHz, a phase noise of -101.13 dBc/Hz measured at an offset frequency of 1 MHz, and a power consumption of 80 mW is achieved. For the whole system, designed with the UMC 0.18 μm Mixed Mode and RF CMOS technology, the clock generator achieves a frequency range from 1.7 to 2.25 GHz, with a delay accuracy of 1.86 ps and a capacitive unbalanced compensation for errors up to 15 fF. The power consumption of the clock generator is 150 mW.