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Tolerância a Falhas na Rede em Chip SPINoSys
(Universidade Federal do Rio Grande do NorteBrasilUFRNCiência da Computação, 2017)
With the advances in the manufacture of integrated circuits, chips with multiple processing
cores appeared. With the increase in the number of cores within a single chip, the use
of buses as solution for communication ...
Design space exploration of hybrid topologies and DVFS in on-chip communication networks
(Universidade Federal de Santa MariaBrasilUFSMCentro de Tecnologia, 2021-09-24)
Multi-Processor Systems-on-Chip (MPSoCs) have been established as the standard
platform for high-performance applications in the semiconductor industry.
With an increasing number of Processing Elements (PEs) within a ...
Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys
(Universidade Federal do Rio Grande do NorteBRUFRNPrograma de Pós-Graduação em Sistemas e ComputaçãoCiência da Computação, 2012-03-30)
It bet on the next generation of computers as architecture with multiple processors and/or
multicore processors. In this sense there are challenges related to features interconnection, operating
frequency, the area on ...
Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys
(Universidade Federal do Rio Grande do NorteBRUFRNPrograma de Pós-Graduação em Sistemas e ComputaçãoCiência da Computação, 2008-04-11)
The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence ...
Dynamic and static task mapping in a network-on-chip using machine learning techniques
(Universidade Federal de Santa MariaBrasilUFSMCentro de Tecnologia, 2015-12-16)