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Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description

IGNACIO ALGREDO BADILLO; CLAUDIA FEREGRINO URIBE; RENE ARMANDO CUMPLIDO PARRA; MIGUEL MORALES SANDOVAL (IEICE Transactions on Information and Systems, 2008)

Using CafeOBJ to implement a reduction strategy in the context of hardware/software partitioningUsing CafeOBJ to implement a reduction strategy in the context of hardware/software partitioningUsing CafeOBJ to implement a reduction strategy in the context of hardware/software partitioning

Silva, André Luís Meneses; Menezes, Manoel Messias; Silva, Leila (Elsevier, 2014)

Implementação em hardware de um módulo de tradução binária para uma arquitetura reconfigurávelHardware implementation of a binary translation module for a reconfigurable architecture

Lazzarotto, Alexis Anton (2011)

Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description

IGNACIO ALGREDO BADILLO; CLAUDIA FEREGRINO URIBE; RENE ARMANDO CUMPLIDO PARRA; MIGUEL MORALES SANDOVAL (IEICE Transactions on Information and Systems, 2008)

AES IP Core: hardware criptográfico

Mesquita, Leonardo [UNESP]; Universidade Estadual Paulista (Unesp) (Universidade Estadual Paulista (Unesp), 2016-12-15)

This work developed a FPGA-based cryptographic hardware. The encryption algorithm used was AES-256 implemented in VHDL. The project aimed a balance between hardware footprint and processing speed. Also, through the UART ...

FPGA hardware linear regression implementation using fixed-point arithmetic

Universidade Estadual Paulista (Unesp); University of Limerick (2019-08-26)

In this paper, a hardware design based on the field programmable gate array (FPGA) to implement a linear regression algorithm is presented. The arithmetic operations were optimized by applying a fixed-point number ...

Implementação em hardware da arquitetura do computador hipotético CESARHardware implementation of the CESAR hypothetical computer architecture

Orth, Gustavo Kaefer (2011)

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Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description

Using CafeOBJ to implement a reduction strategy in the context of hardware/software partitioningUsing CafeOBJ to implement a reduction strategy in the context of hardware/software partitioningUsing CafeOBJ to implement a reduction strategy in the context of hardware/software partitioning

Implementação em hardware de um módulo de tradução binária para uma arquitetura reconfigurávelHardware implementation of a binary translation module for a reconfigurable architecture

Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description

AES IP Core: hardware criptográfico

FPGA hardware linear regression implementation using fixed-point arithmetic

Implementação em hardware da arquitetura do computador hipotético CESARHardware implementation of the CESAR hypothetical computer architecture

Metodologia para criação de um sistema de hardware evolutivo em fpga utilizando o processador Nios II

Adaptive Function Segmentation Methodology for Resources Optimization of Hardware-Based Function Evaluators

Adaptive Function Segmentation Methodology for Resources Optimization of Hardware-Based Function Evaluators

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Filtros

Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description

Using CafeOBJ to implement a reduction strategy in the context of hardware/software partitioningUsing CafeOBJ to implement a reduction strategy in the context of hardware/software partitioningUsing CafeOBJ to implement a reduction strategy in the context of hardware/software partitioning

Implementação em hardware de um módulo de tradução binária para uma arquitetura reconfigurávelHardware implementation of a binary translation module for a reconfigurable architecture

Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description

AES IP Core: hardware criptográfico

FPGA hardware linear regression implementation using fixed-point arithmetic

Implementação em hardware da arquitetura do computador hipotético CESARHardware implementation of the CESAR hypothetical computer architecture

Metodologia para criação de um sistema de hardware evolutivo em fpga utilizando o processador Nios II

Adaptive Function Segmentation Methodology for Resources Optimization of Hardware-Based Function Evaluators

Adaptive Function Segmentation Methodology for Resources Optimization of Hardware-Based Function Evaluators