Actas de congresos
FPGA hardware linear regression implementation using fixed-point arithmetic
Fecha
2019-08-26Registro en:
Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019.
10.1145/3338852.3339853
2-s2.0-85073410567
Autor
Universidade Estadual Paulista (Unesp)
University of Limerick
Institución
Resumen
In this paper, a hardware design based on the field programmable gate array (FPGA) to implement a linear regression algorithm is presented. The arithmetic operations were optimized by applying a fixed-point number representation for all hardware based computations. A floating-point number training data point was initially created and stored in a personal computer (PC) which was then converted to fixed-point representation and transmitted to the FPGA via a serial communication link. With the proposed VHDL design description synthesized and implemented within the FPGA, the custom hardware architecture performs the linear regression algorithm based on matrix algebra considering a fixed size training data point set. To validate the hardware fixed-point arithmetic operations, the same algorithm was implemented in the Python language and the results of the two computation approaches were compared. The power consumption of the proposed embedded FPGA system was estimated to be 136.82 mW.