| dc.contributor | Figueroa-Toro, Miguel | |
| dc.contributor | Universidad de Concepción | |
| dc.creator | Carvajal-Barrera, Gonzalo Andrés | |
| dc.date | 2017-04-06T19:44:20Z | |
| dc.date | 2022-08-18T23:20:54Z | |
| dc.date | 2017-04-06T19:44:20Z | |
| dc.date | 2022-08-18T23:20:54Z | |
| dc.date | 2015 | |
| dc.date | 2013 | |
| dc.date.accessioned | 2023-08-21T21:32:20Z | |
| dc.date.available | 2023-08-21T21:32:20Z | |
| dc.identifier | http://creativecommons.org/licenses/by-nc-nd/3.0/cl/ | |
| dc.identifier | https://hdl.handle.net/10533/181492 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/8284940 | |
| dc.description | Ethernet is widely recognized as an attractive networking technology for next-generation distributed
embedded systems in multiple domains such as avionics, automotive, industrial control,
medical devices, among others. High bandwidth, low-cost, and easy integration with traditional
networking infrastructures make Ethernet a potential solution to the challenges for future
embedded applications. However, due to the intrinsic competitive approach of the standard,
Ethernet components require specific modifications and hardware support to provide the strict
timing guarantees required for safety-critical applications. While the literature reports multiple
mechanisms to coordinate the exchange of messages in Ethernet networks, the design, implementation,
and evaluation of the necessary hardware components remains mostly unexplored. This
lack of experimental validation is hindering the adoption and further developments in real-time
networking.
This dissertation explores the challenges related to the design and implementation of Ethernet
components based on timing specifications. In particular, the work focuses on providing the
hardware infrastructure for the Network Code framework, which defines a communication model
based on Time Division Multiple Access (TDMA) arbitration that is well-suited for safety-critical
applications. The ultimate result of this research is the release of Atacama, the first open-source
framework based on reconfigurable hardware for mixed-criticality communication in multisegmented
Ethernet networks. Atacama uses highly-specialized modules for the execution of
Network Code schedules, delivering low and predictable latency for real-time frames in multi-hop
topologies. The modules seamlessly integrate with a standard Ethernet infrastructure operating
with best-effort traffic. The result is an integral framework that covers from the formal definition
of the communication model, all the way down to the implementation of the prototypes, which
enable easy optimization of devices for specific application scenarios, and rapid prototyping of
new protocol characteristics. Researchers can use the open-source design to verify our results and
build upon the framework, which aims to accelerate the development, validation, and adoption
of Ethernet-based solutions in real-time applications. | |
| dc.description | PFCHA-Becas | |
| dc.description | Doctorado en Ciencias de la Ingeniería Mención en Ingeniería Eléctrica | |
| dc.description | 81p. | |
| dc.description | PFCHA-Becas | |
| dc.description | TERMINADA | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.relation | instname: Conicyt | |
| dc.relation | reponame: Repositorio Digital RI2.0 | |
| dc.relation | instname: Conicyt | |
| dc.relation | reponame: Repositorio Digital RI2.0 | |
| dc.relation | handle/10533/108040 | |
| dc.relation | info:eu-repo/grantAgreement/PFCHA-Becas/RI20 | |
| dc.relation | info:eu-repo/semantics/dataset/hdl.handle.net/10533/93488 | |
| dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Chile | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.title | Network devices for hard real-time communicatión on switched ethernet | |
| dc.type | Tesis Doctorado | |
| dc.type | info:eu-repo/semantics/doctoralThesis | |
| dc.type | info:eu-repo/semantics/publishedVersion | |
| dc.type | Tesis | |
| dc.coverage | Concepción | |
