As process technology continues to shrink, Process Variations and Aging effects have an increasing impact on the reliability and performance of manufactured circuits. Aging effects, namely due to Negative Bias Temperature Instability (NBTI) produce performance degradation as time progresses. This degradation rate depends on a) Operational conditions (e.g., VDD, Temperature and time of electrical stress on MOS transistors) and b) Static technological parameters defined in the fabrication process. Moreover, performance of electronic systems for safety-critical applications which operate for many years in harsh environments are more prompt to be impacted by aging. In order to guarantee a safe operation in advanced technologies, aging monitoring should be performed on chip using built-in aging sensors. The purpose of this work is to present a methodology to determine the correct location for aging sensor insertion, considering the combined impact of process variations (PV) and aging effects (namely due to NBTI). In order to implement the methodology, a path-based statistical timing analysis framework and tools have been developed. It is shown that delay path reordering, associated with PV and aging, may justify the insertion of a few additional sensors, to cover abnormal delays of signal paths that become critical, under long system operation (e.g., 10 years).