On-chip interconnections play a key role in the design and implementation of current and future clock generation and distribution networks used for synchronization of high-performance integrated systems; therefore, an accurate modeling (i.e. electrical representation) of the interconnections used in this type of networks is essential and it represents an important research area. In global and local clock networks, the interconnection lines in combination with a set of gain stages are used to simultaneously generate and distribute high-frequency synchronization signals throughout the integrated circuit. Therefore, in the design of this type of networks, the electrical equivalent circuit model provides important information about the characteristics of the interconnections used in the implementation; then, based on this information, an accurate design of the gain, compensation, and output stages can be carried out. Traditionally, the interconnection lines used in the design of integrated systems have been represented by electrical equivalent circuit models obtained from basic analytical expressions and technology parameters provided by the foundry; however, the accuracy of these models is limited specially for the representation of interconnections operating within the Gigahertz (GHz) frequency range where the frequency dependence of the interconnect parameters can not be neglected. Therefore, in the design of high-speed integrated systems (e.g. clock generation and distribution networks) it is necessary to implement accurate equivalent circuit models for the representation of the interconnections; for this reason, in this thesis the establishment of a modeling methodology that allows circuit designers to perform an accurate representation of the interconnection lines used in the design and implementation of global and local clock networks are presented. The modeling methodology is developed directly from S-parameter measurements of fabricated test structures and includes: the interconnect parameter extraction procedure, the equivalent circuit model selection, and the determination of the minimum number of sections required in the equivalent circuit for the accurate representation of interconnects of certain lengths within specific frequency ranges, while considering the frequency-dependent nature of the associated parameters.