In the last few years, the focus on the vision systems research has increased due to multiple demands of performance, power consumption and integration area. Hence, a need for the design and manufacturing of Intelligent Sensors systems has arised. A particular type of Intelligent Sensors are Vision Chips, which have demonstrated to be ecient facing image processing and real time pro- cessing issues. Vision Chips are classied as intelligent sensors because their main goals are photodetection and image processing, and both assignments are performed in a single chip. Currently, the development of two-dimensional arrays of sensors is mainly focused on biomedical, astronomical and military applications. Recently, vision chips based on CMOS image sensors are competing with the Charged Coupled Devices (CCDs). Since CCD's fabrication process is com- plex and expensive, the studies on CMOS Image Sensors have considerably increased. Therefore, both CCD and CMOS have their particular advantages, which makes the convenience of the use of one over the other depending on the task requirements. Consequently it is not possible to claim about a dominant tech- nology over its counterpart. Besides of the sensor type, it is of great importance having amplifying and l- tering stages whose fulll required design constraints like power consumption, area, supply voltage, speed, cost, impulsive noise, shot noise, Fixed Pattern Noise (FPN), thermal noise and image quality. In that fashion, a large number of Pixel and Readout topologies have been developed. Similarly, several studies, analyses and comparatives about how ltering certain types of noise on corrupted images have been also reported. This work presents the design and implementation of a Vision Chip using pre- processing in-pixel low-power techniques with digital controlled access to the pixel array. Also, the settling of the basis to future work is established by material properties and features to optimize photodetectors design.