| dc.contributor | Aguilera-Galicia, Cuauhtémoc R. | |
| dc.creator | Figueroa-Vázquez, Cristian F. | |
| dc.date | 2020-10-14T01:16:02Z | |
| dc.date | 2020-10-14T01:16:02Z | |
| dc.date | 2020-08 | |
| dc.date.accessioned | 2023-07-21T22:10:43Z | |
| dc.date.available | 2023-07-21T22:10:43Z | |
| dc.identifier | Figueroa-Vázquez, C. F. (2020). A 0.18um CMOS linear Voltage-to-Time Converter for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle Oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO | |
| dc.identifier | https://hdl.handle.net/11117/6365 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7761111 | |
| dc.description | This document presents a 0.18 um CMOS process highly-linear Voltage-to-Time Converter (VTC) design that can operate at a low voltage of 1.8 V across PVT corners and with the power consumption of less than 13 uW and linearity error less than 1%. The VTC was designed to work at a minimum of 1.68 V and accepts a maximum clock frequency of 900 MHz; to reduce non-linear behavior a symmetric load and current starved inverter configuration was proposed. This circuit was designed using TSMC 0.18 um CMOS process technology. | |
| dc.description | ITESO, A. C. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | ITESO | |
| dc.rights | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | |
| dc.subject | Analog to Digital Converter | |
| dc.subject | Voltage to Time Converter | |
| dc.subject | Digital to Analog Converter | |
| dc.title | A 0.18um CMOS linear Voltage-to-Time Converter for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle Oriented to Audio Applications | |
| dc.type | info:eu-repo/semantics/academicSpecialization | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
