dc.contributorCarrasco-Navarro, Rocío
dc.creatorSánchez-Martínez, César A.
dc.date2021-07-16T23:04:32Z
dc.date2021-07-16T23:04:32Z
dc.date2020-12
dc.date.accessioned2023-07-21T22:10:12Z
dc.date.available2023-07-21T22:10:12Z
dc.identifierSánchez-Martínez, C. A. (2020). Machine Learning Techniques for Electrical Validation Enhancement Processes. Trabajo de obtención de grado, Maestría en Ciencia de Datos. Tlaquepaque, Jalisco: ITESO
dc.identifierhttps://hdl.handle.net/11117/7451
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7760940
dc.descriptionPost-Silicon system margin validation consumes a significant amount of time and resources. To overcome this, a reduced validation plan for derivative products has previously been used. However, a certain amount of validation is still needed to avoid escapes, which is prone to subjective bias by the validation engineer comparing a reduced set of derivative validation data against the base product data. Machine Learning techniques allow, to perform automatic decisions and predictions based on already available historical data. In this work, we present an efficient methodology implemented with Machine Learning to make an automatic risk assessment decision and eye margin estimation measurements for derivative products, considering a large set of parameters obtained from the base product. The proposed methodology yields a high performance on the risk assessment decision and the estimation by regression, which translates into a significant reduction in time, effort, and resources.
dc.formatapplication/pdf
dc.languageeng
dc.publisherITESO
dc.rightshttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf
dc.subjectElectrical Validation
dc.subjectMachine Learning
dc.subjectSupport Vector Machine
dc.subjectDecision Tree
dc.subjectArtificial Neural Network
dc.subjectLogit
dc.subjectElectrical Testing
dc.subjectLinear Regression
dc.subjectEqualizer
dc.subjectSystem Marginality Validation
dc.subjectSATA
dc.subjectPost-Silicon Validation
dc.titleMachine Learning Techniques for Electrical Validation Enhancement Processes
dc.typeinfo:eu-repo/semantics/masterThesis
dc.typeinfo:eu-repo/semantics/acceptedVersion


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