A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

dc.creatorRangel-Patiño, Francisco E.
dc.creatorViveros-Wacher, Andrés
dc.creatorRayas-Sánchez, José E.
dc.creatorDuron-Rosales, Ismael
dc.creatorVega-Ochoa, Édgar A.
dc.creatorHakim, Nagib
dc.creatorLópez-Miralrio, Enrique
dc.date2020-06-12T21:29:40Z
dc.date2020-06-12T21:29:40Z
dc.date2020-06
dc.date.accessioned2023-07-21T22:03:46Z
dc.date.available2023-07-21T22:03:46Z
dc.identifierF.E. Rangel-Patiño, A. Viveros-Wacher, J.E. Rayas-Sánchez, I. Durón-Rosales, E.A. Vega-Ochoa, N. Hakim, and E. López-Miralrio, A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation, IEEE Trans. Emerging Topics Computing,8( 2): 453-463, Apr.-Jun. 2020. DOI: 10.1109/TETC.2017.2757937
dc.identifier2376-4562
dc.identifierhttps://hdl.handle.net/11117/6236
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7758564
dc.descriptionThere is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.
dc.descriptionITESO, A.C.
dc.formatapplication/pdf
dc.languageeng
dc.publisherIEEE
dc.rightshttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf
dc.subjectBit-error-rate
dc.subjectDoE
dc.subjectEqualization
dc.subjectEye-diagram
dc.subjectHigh-speed serial I/O
dc.subjectInterconnects
dc.subjectJitter
dc.subjectKriging
dc.subjectOptimization
dc.subjectPost-Si validation
dc.subjectReceiver
dc.subjectSerDes
dc.subjectTransmitter
dc.titleA Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/acceptedVersion


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