| dc.contributor | Aguilera-Galicia, Cuauhtémoc R. | |
| dc.creator | Garza-Pérez, Raymundo | |
| dc.date | 2022-01-10T21:15:44Z | |
| dc.date | 2022-01-10T21:15:44Z | |
| dc.date | 2021-07 | |
| dc.date.accessioned | 2023-07-21T22:03:25Z | |
| dc.date.available | 2023-07-21T22:03:25Z | |
| dc.identifier | Garza-Pérez, R. (2021). Registro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicas. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | |
| dc.identifier | https://hdl.handle.net/11117/7691 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7758422 | |
| dc.description | This document presents the design of a successive approximation register (SAR) and a digital to analog converter (DAC). The two circuits are designed, synthesized, and implemented in layout using TSMC 180nm technology. The DAC has a Charge-Scaling Capacitors architecture and uses a switching scheme different to the conventional one, which improves the power consumption of the circuit. These modules are used in a low power 10-bit ADC and are designed for Biomedical applications. The SAR design is synthesized using a clock with a frequency of 250 MHz, the total power consumption of the SAR is 22045.030 uW. A testbench is designed to verify the functionality of the SAR by testing several cases of interest. The base capacitance of the DAC is 1 pF. The functionality of the DAC is tested using a mixed signal simulator and a testbench with the required circuit. This also includes the Verilog model of the SAR block. The testbench is able to apply single conversions test case and a ramp-test case, in which all the possible inputs to the DAC are tested sequentially. | |
| dc.description | ITESO, A. C. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | ITESO | |
| dc.rights | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | |
| dc.title | Registro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicas | |
| dc.type | info:eu-repo/semantics/academicSpecialization | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
