dc.contributor | Martínez-Guerrero, Esteban | |
dc.creator | Hernández-Flores, Jaime G. | |
dc.date | 2020-11-05T21:26:11Z | |
dc.date | 2020-11-05T21:26:11Z | |
dc.date | 2020-08 | |
dc.date.accessioned | 2023-07-21T21:55:43Z | |
dc.date.available | 2023-07-21T21:55:43Z | |
dc.identifier | Hernández-Flores, J. G. (2020). Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | |
dc.identifier | https://hdl.handle.net/11117/6387 | |
dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7755356 | |
dc.description | This document presents the design of a time amplifier circuit in 0.18 m CMOS process with a supply voltage of 1.8 V. Simulation results performed with typical process parameters, nominal supply voltage, room temperature and an operating frequency of 200 KHz, show a time gain of 200, with an error of less than 7%. The power consumption of the designed circuit is 26 W. The circuit can receive signals with a time difference from 10 ps to 4.7 nS. The layout dimension is 149.985 m x 168.536 m, with an area of 25.3 nm2. | |
dc.description | ITESO, A. C. | |
dc.format | application/pdf | |
dc.language | eng | |
dc.publisher | ITESO | |
dc.rights | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | |
dc.subject | Time Amplifier | |
dc.title | Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology | |
dc.type | info:eu-repo/semantics/academicSpecialization | |
dc.type | info:eu-repo/semantics/acceptedVersion | |