dc.creatorJuarez-Abad J.A., Sandoval-Garcia A.P., Linares-Flores J., Guerrero-Castellanos J.F., Banuelos-Sanchez P., Contreras-Ordaz M.A.
dc.date2020-12-11T06:46:42Z
dc.date2020-12-11T06:46:42Z
dc.date2019
dc.date.accessioned2023-07-21T20:22:11Z
dc.date.available2023-07-21T20:22:11Z
dc.identifier2-s2.0-85051629200
dc.identifierhttp://repositorio.udlap.mx/xmlui/handle/123456789/13592
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7745715
dc.descriptionhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85051629200&doi=10.1109%2fTII.2018.2865445&partnerID=40&md5=26321cfa03f1e8d2d59fe1cebaf29af3
dc.sourceIEEE Transactions on Industrial Informatics
dc.titleFPGA Implementation of Passivity-Based Control and Output Load Algebraic Estimation for Transformerless Multilevel Active Rectifier
dc.typeArticle


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