dc.creatorCampos Cantón, Eric
dc.creatorCampos Cantón, Isaac
dc.creatorRosu Barbus, Haret-Codratian
dc.date2018-03-21T23:42:18Z
dc.date2018-03-21T23:42:18Z
dc.date2013
dc.date.accessioned2023-07-17T22:04:49Z
dc.date.available2023-07-17T22:04:49Z
dc.identifierhttp://hdl.handle.net/11627/3455
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7544122
dc.description"A dynamically reconfigurable linear core logic gate is a device that allows logical outputs dependent upon configurable parameters set within device. The device is comprised of three blocks: The first block receives at least one input signal and determines whether the signal o signals are low or high in comparison with a threshold reference signal. The second block sums the logic signals of the first block with an offset signal. The third block determines if the sum realized in the second block is a low or high by checking whether the sum falls within a predetermined interval."
dc.formatapplication/pdf
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.rightsAcceso Abierto
dc.subjectH03K19/173
dc.subjectH03K19/1733
dc.subjectH03K25/04
dc.subjectCIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA
dc.titleReconfigurable dynamical logic gate with linear core
dc.typepatente


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