Fixed reference frame phase-locked loop (FRF-PLL) for unbalanced line voltage conditions

dc.creatorEscobar Valderrama, Gerardo
dc.creatorTorres Olguín, Raymundo Enrique
dc.creatorMartínez Montejano, Misael Francisco
dc.date2018-06-08T23:34:38Z
dc.date2018-06-08T23:34:38Z
dc.date2008-10
dc.date.accessioned2023-07-17T22:04:06Z
dc.date.available2023-07-17T22:04:06Z
dc.identifierhttp://hdl.handle.net/11627/3955
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/7543814
dc.description"The present invention relates to a system to implement a phase-locked loop (PLL) which is able to provide an estimation of the angular frequency, and both the positive and negative sequences of the fundamental component of a three-phase signal. These sequences are provided in fixed reference frame coordinates."
dc.formatapplication/pdf
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.rightsAcceso Abierto
dc.subjectG01R25/00
dc.subjectG06F19/00
dc.subjectH03L7/08
dc.subjectMATEMÁTICAS
dc.titleFixed reference frame phase-locked loop (FRF-PLL) for unbalanced line voltage conditions
dc.typepatente


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