dc.creator | Lomelí-Illescas, Ismael | |
dc.creator | Solís-Bustos, Sergio A. | |
dc.creator | Martínez-Sánchez, Víctor H. | |
dc.creator | Rayas-Sánchez, José E. | |
dc.date.accessioned | 2022-10-14T12:13:03Z | |
dc.date.available | 2022-10-14T12:13:03Z | |
dc.date.issued | 2016-10 | |
dc.identifier | I. Lomelí-Illescas, S. A. Solís-Bustos, V. H. Martínez-Sánchez, and J. E. Rayas-Sánchez, “Synthesis tool for automatic layout generation of analog structures,” in IEEE ANDESCON Proc., Arequipa, Peru, Oct. 2016, pp. 1-4. | |
dc.identifier | 978-1-5090-2532-9 | |
dc.identifier | http://hdl.handle.net/11117/5943 | |
dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/4235806 | |
dc.language | eng | |
dc.publisher | IEEE | |
dc.rights | http://quijote.biblio.iteso.mx/licencias/TodosLosDerechosReservados.pdf | |
dc.subject | Analog Layout | |
dc.subject | Integrated Circuit | |
dc.subject | CAD Tool | |
dc.subject | Nanometric Analog Layout | |
dc.title | Synthesis tool for automatic layout generation of analog structures | |
dc.type | info:eu-repo/semantics/conferencePaper | |