Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation

dc.creatorRangel-Patiño, Francisco E.
dc.creatorRayas-Sánchez, José E.
dc.creatorVega-Ochoa, Edgar A.
dc.creatorHakim, Nagib
dc.date.accessioned2019-08-29T20:39:41Z
dc.date.accessioned2022-10-14T12:12:09Z
dc.date.available2019-08-29T20:39:41Z
dc.date.available2022-10-14T12:12:09Z
dc.date.created2019-08-29T20:39:41Z
dc.date.issued2018-03
dc.identifierF. E. Rangel-Patiño, J. E. Rayas-Sánchez, E. A. Vega-Ochoa and N. Hakim, "Direct optimization of a PCI express link equalization in industrial post-silicon validation," 2018 IEEE 19th Latin-American Test Symposium (LATS), Sao Paulo, 2018, pp. 1-6. doi: 10.1109/LATW.2018.8347238
dc.identifier2373-0862
dc.identifierhttp://hdl.handle.net/11117/6001
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/4235677
dc.languageeng
dc.publisherIEEE
dc.rightshttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf
dc.subjectChannel
dc.subjectCrosstalk
dc.subjectCTLE
dc.subjectEqualization Maps
dc.subjectEye Diagram
dc.subjectFIR
dc.subjectHigh-speed Links
dc.subjectISI
dc.subjectJitter
dc.subjectOptimization
dc.subjectPCIe
dc.subjectPost-silicon Validation
dc.subjectReceiver
dc.subjectSignal Integrity
dc.subjectTransmitter
dc.subjectTuning
dc.titleDirect Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation
dc.typeinfo:eu-repo/semantics/article


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