System Margining Surrogate-Based Optimization in Post-Silicon Validation

dc.creatorRangel-Patiño, Francisco E.
dc.creatorChávez-Hurtado, José L.
dc.creatorViveros-Wacher, Andrés
dc.creatorRayas-Sánchez, José E.
dc.date.accessioned2019-07-23T18:00:54Z
dc.date.accessioned2022-10-14T12:11:10Z
dc.date.available2019-07-23T18:00:54Z
dc.date.available2022-10-14T12:11:10Z
dc.date.created2019-07-23T18:00:54Z
dc.date.issued2017-09
dc.identifierF. E. Rangel-Patiño, J. L. Chávez-Hurtado, A. Viveros-Wacher, J. E. Rayas-Sánchez, and N. Hakim, “System margining surrogate-based optimization in post-silicon validation,” IEEE Trans. Microwave Theory Techn., vol. 65, no. 9, pp. 3109-3115, Sep. 2017. DOI: 10.1109/TMTT.2017.2701368
dc.identifier0018-9480
dc.identifierhttp://hdl.handle.net/11117/5947
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/4235527
dc.languageeng
dc.publisherIEEE
dc.rightshttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf
dc.subjectDoE
dc.subjectEqualization
dc.subjectEye Diagram
dc.subjectHSIO
dc.subjectKriging
dc.subjectNeural Network
dc.subjectOptimization
dc.subjectPost-silicon Validation
dc.subjectSurrogate Models
dc.subjectReceiver
dc.subjectSupport Vector Machines
dc.titleSystem Margining Surrogate-Based Optimization in Post-Silicon Validation
dc.typeinfo:eu-repo/semantics/article


Este ítem pertenece a la siguiente institución