Machine Learning Techniques and Optimization Approaches for Analog Validation and Testing

dc.contributorRayas-Sánchez, José E.
dc.creatorViveros-Wacher, Andrés
dc.date.accessioned2021-01-11T19:46:50Z
dc.date.accessioned2022-10-14T12:06:41Z
dc.date.available2021-01-11T19:46:50Z
dc.date.available2022-10-14T12:06:41Z
dc.date.created2021-01-11T19:46:50Z
dc.date.issued2020-12
dc.identifierViveros-Wacher, Andrés (2020) Machine Learning Techniques and Optimization Approaches for Analog Validation and Testing, Tesis de doctorado, Doctorado en Ciencias de la Ingeniería. Tlaquepaque, Jalisco: ITESO.
dc.identifierhttps://hdl.handle.net/11117/6462
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/4234862
dc.languageeng
dc.publisherITESO
dc.rightshttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf
dc.subjectOptimization
dc.subjectAnalog Faults
dc.subjectMachine Learning
dc.subjectJitter Tolerance
dc.subjectBit Error Rate
dc.titleMachine Learning Techniques and Optimization Approaches for Analog Validation and Testing
dc.typeinfo:eu-repo/semantics/doctoralThesis


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