Dual-Core embedded implementation of the SISO adaptive predictive control

Abstract

The SISO Adaptive Predictive Control (APC) algorithm is implemented on a Dual-Core embedded system. The Predictive control strategy is implemented on one of the cores available on the ZYNQ processing system, and the Adaptation Mechanism is implemented on the second core. The implementation can be thought of as two independent applications running simultaneously. However, these are not completely independent. The Predictive Control model is updated on every sampling interval with new parameters generated by the Adaptation mechanism that better fit the response of the system under control. To correctly synchronize the two applications, a Master-Slave architecture was chosen for the communication between the two cores. The core running the predictive control algorithm was assigned the role of the master because it had a longer execution time for every sampling period. This first core acted as the master and orchestrated the flow of data between the two cores and the actions taken by the second core. The second core, which computes the adaptation mechanism, acted as the slave, as it only performed operations when it received a message from the first core at specific times during a sampling period. Further optimization was achieved by using in-line Assembly code, which makes it possible to take advantage of the processor architecture and implement optimal subroutines for a particular application. The low-level optimizations improved execution time by reducing clock cycle counts and reducing the use of external memory for temporary variables. These optimizations resulted in a speedup of up to 3x when compared to the latest embedded implementation of the APC algorithm reported in the literature.