Because of their very large integration capabilities and continuous scaling, the CMOS devices are the basic element in the currentintegrated circuits. Their scaling up to sub-micrometric scale presents advantages like diminution of power consumption, faster devices and a larger level of integration. But the physics limitations begin to be important at these dimensions, anomalous effects like hot electrons, leakage currents and punch through, among others, appear. These effects can be reduced if, at the source/drain region, shallow junctions are obtained with junction depth (xj) less than 200 nm. To achieve this goal, new junction fabrication methods, which include pre-amorphization [S.D. Kim, C.M. Park, J.C.S. Woo, Formation and control of box-shaped ultra-shallow junction using laser annealing and pre-amorphization implantation, Solid State Electron. 49 (2005) 131–135] are required. Other alternative techniques that do not require ion implantation [T. Uchino, P. Ashburn, Y. Kiyota, T. Shiba, A CMOS-compatible rapid vapor-phase doping process for CMOS scaling, IEEE Trans. Electron Devices 51(1) (2004) 14–19.], in order to prevent surface crystal damage and as a consequence the inhibition of boron interstitial clusters and {3 1 1} defects [R.T. Crosby, K.S. Jones, M.E. Law, L. Radic, Dislocation loops in silicon–germanium alloys: the source of interstitials, Appl. Phys. Lett. 87 (192111) (2005) 1–3.], which are the trigger of the ‘‘transient enhanced diffusion’’ (TED) process are used. In this essay, it is shown that rapid thermal process, allow the fabrication of very shallow junctions with a xj less than 300nm by using with high energies and high doses of boron/BF2 ions implantation. By this way the slow dissolution of the dislocation loops, present at the end of range (EOR) of the implanted boron, allow this process. These obtained junctions are compared with those prepared by using the spin on doping (SOD) technique. The diffusion profiles obtained by both processes and their electrical properties are measured and compared for their application as S–D regions in a current CMOS process.