Tese
Modulação space vector para conversores multiníveis com células assimétricas em cascata sob condições de faltas
Fecha
2015-10-09Registro en:
CARNIELUTTI, Fernanda de Morais. Space vector modulation for cascaded multilevel converters
with asymmetric cells under fault conditions. 2015. 197 f. Tese (Doutorado em Engenharia Elétrica) - Universidade Federal de Santa Maria, Santa Maria, 2015.
Autor
Carnielutti, Fernanda de Morais
Institución
Resumen
This Thesis proposes a Space Vector Modulation for cascaded miltilevel converters with
asymmetric cells under normal conditions and with faults in the power cells, avoiding
converter saturation as much as possible. The switching state vectors and the voltage
references are represented in the output line-to-line voltages coordinate system. Under
this representation, the switching state vectors have only integer entries, easing the implementation
of the proposed algorithm. The modulation is developed in a way such as
to guarantee that the higher voltage cells switch at low frequency by the choice of only
one vector per switching period, minimizing the switching losses. For the lower voltage
cells (1pu), that switch with PWM, three algorithms were developed for defining the switching
sequences: (i) offline, (ii) online and (iii) hybrid, where a carrier-based geometrical
modulation and the SV are mixed in a simple and unified approach. The algorithm is
described in a generic way, for converters with any number of levels, and then, simulation
and experimental results are shown for, respectively, cascaded miltilevel converters with
asymmetric cells with DC bus voltages ratio of 1:2:4pu and 1:2pu. The algorithm does
not use conventional separation lines to find where the multiple references for the power
cells are located inside the SV diagram. It also avoids converter saturation and, when it is
unavoidable, detects its occurrence and changes the operation mode to overmodulation.
This one is treated as a modification of the orignal algorithm, allowing the converter to
operate with a wider range of modulation indexes and fault conditions. It is shown that
two overmodulation modes can occur: in the first, there is still an area inside the SV diagram
where overmodulation is avoided, and, in the second, the converter overmodulates
during almost all the time. Modulation strategies are proposed for both cases, including
the insertion of a bandpass filter in the second case, so as to minimize the distortions and
unbalances that arise on the converter output line-to-line voltages during this operation
mode. For the overmodulation, simulation and experimental results are also shown for
cascaded miltilevel converters with asymmetric cells with DC bus voltages ratio of 1:2:4pu
and 1:2pu. Finally, the final conclusions are drawn and future works are proposed.