Técnicas para redução de consumo em conversores analógico-digitais por aproximação sucessiva e compartilhamento de carga

Abstract

New trends and emerging technologies motivate the design of analog-to-digital converters (ADCs) which must fit in increasingly constrained environments. Within this context, one design metric which is constantly forced towards reduction is the power consumption, leading the designers to come up with improvements in both the architecture and circuit levels. This work aims to push forward the energy efficiency of the successive approximation charge sharing ADC, which is a relatively new and unexplored architecture. Therefore, three complete ADCs are designed throughout this work, each one bringing novelties that help decreasing the power consumption. The techniques devised here include novel manners of dealing with the tracking of the input signal and a circuit to reduce power drained in the pre-charge cycle. Also, three different architectures of digital controller for this ADC topology are designed. Moreover, a novel bootstrapping switch circuit is presented, which provides lower devices-count and a extremely high energy efficiency.