Actas de congresos
Design of CMOS current-mode multiplier-divider circuit for type-2 FLC applications
Fecha
2015-01-01Registro en:
2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings.
10.1109/LASCAS.2015.7250476
2-s2.0-84945156769
9186632586177726
9338079447464341
0000-0001-5246-4438
Autor
Universidade Estadual Paulista (Unesp)
Institución
Resumen
The design of a low voltage current-mode CMOS multiplier/divider circuit is presented in this paper. This circuit is used to implement the type-reducer block of Type-2 Fuzzy Logic Controller chip. The simulation results of multiplier/divider circuit have been done in CMOS 0.35μm technology through Pspice software using a single supply voltage of 1.8V.