dc.contributor | Universidade Estadual Paulista (Unesp) | |
dc.date.accessioned | 2018-12-11T17:25:58Z | |
dc.date.available | 2018-12-11T17:25:58Z | |
dc.date.created | 2018-12-11T17:25:58Z | |
dc.date.issued | 2015-01-01 | |
dc.identifier | 2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings. | |
dc.identifier | http://hdl.handle.net/11449/177557 | |
dc.identifier | 10.1109/LASCAS.2015.7250476 | |
dc.identifier | 2-s2.0-84945156769 | |
dc.identifier | 9186632586177726 | |
dc.identifier | 9338079447464341 | |
dc.identifier | 0000-0001-5246-4438 | |
dc.description.abstract | The design of a low voltage current-mode CMOS multiplier/divider circuit is presented in this paper. This circuit is used to implement the type-reducer block of Type-2 Fuzzy Logic Controller chip. The simulation results of multiplier/divider circuit have been done in CMOS 0.35μm technology through Pspice software using a single supply voltage of 1.8V. | |
dc.language | eng | |
dc.relation | 2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings | |
dc.rights | Acesso restrito | |
dc.source | Scopus | |
dc.subject | Interval type-2 fuzzy logic controller | |
dc.subject | Multiplier/divider | |
dc.subject | Type-2 fuzzy logic | |
dc.title | Design of CMOS current-mode multiplier-divider circuit for type-2 FLC applications | |
dc.type | Actas de congresos | |