Actas de congresos
Design of CMOS Current-mode Multiplier-Divider circuit for type-2 FLC Applications
Fecha
2015-01-01Registro en:
2015 Ieee 6th Latin American Symposium On Circuits & Systems (lascas). New York: Ieee, 4 p., 2015.
2330-9954
WOS:000380477800072
9338079447464341
Autor
Universidade Estadual Paulista (Unesp)
Institución
Resumen
The design of a low voltage current-mode CMOS multiplier/divider circuit is presented in this paper. This circuit is used to implement the type-reducer block of Type-2 Fuzzy Logic Controller chip. The simulation results of multiplier/divider circuit have been done in CMOS 0.35 mu m technology through Pspice software using a single supply voltage of 1.8V.