dc.contributor | Universidade Estadual Paulista (Unesp) | |
dc.date.accessioned | 2018-11-27T19:23:16Z | |
dc.date.available | 2018-11-27T19:23:16Z | |
dc.date.created | 2018-11-27T19:23:16Z | |
dc.date.issued | 2015-01-01 | |
dc.identifier | 2015 Ieee 6th Latin American Symposium On Circuits & Systems (lascas). New York: Ieee, 4 p., 2015. | |
dc.identifier | 2330-9954 | |
dc.identifier | http://hdl.handle.net/11449/165265 | |
dc.identifier | WOS:000380477800072 | |
dc.identifier | 9338079447464341 | |
dc.description.abstract | The design of a low voltage current-mode CMOS multiplier/divider circuit is presented in this paper. This circuit is used to implement the type-reducer block of Type-2 Fuzzy Logic Controller chip. The simulation results of multiplier/divider circuit have been done in CMOS 0.35 mu m technology through Pspice software using a single supply voltage of 1.8V. | |
dc.language | eng | |
dc.publisher | Ieee | |
dc.relation | 2015 Ieee 6th Latin American Symposium On Circuits & Systems (lascas) | |
dc.rights | Acesso aberto | |
dc.source | Web of Science | |
dc.subject | component | |
dc.subject | Multiplier/divider | |
dc.subject | Type-2 fuzzy logic | |
dc.subject | Interval type-2 fuzzy logic controller | |
dc.title | Design of CMOS Current-mode Multiplier-Divider circuit for type-2 FLC Applications | |
dc.type | Actas de congresos | |