n-Channel Bulk and DTMOS FinFETs: Investigation of GIDL and Gate Leakage Currents

Abstract

In this work GIDL (Gate Induced Drain Leakage) and Gate Leakage Currents (I-G) have been experimentally investigated for different dimensions of Bulk FinFETs with and without Dynamic Threshold MOS configuration (DTMOS) in linear and saturation regions. The results indicate that Bulk FinFETs present lower gate leakage currents than DTMOS FinFETs. In addition, an opposite I-G behavior of those devices was observed when the channel lengths change. On the other hand, for long channels FinFETs the GIDL effect is lower in devices with DTMOS configuration because the benefit of DTMOS operation becomes higher.