Fixed reference frame phase-locked loop (FRF-PLL) for unbalanced line voltage conditions

GERARDO ESCOBAR VALDERRAMA; RAYMUNDO ENRIQUE TORRES OLGUIN; MISAEL FRANCISCO MARTINEZ MONTEJANO

info:eu-repo/semantics/patent

Registration in:

http://ipicyt.repositorioinstitucional.mx/jspui/handle/1010/1014

http://ipicyt.repositorioinstitucional.mx/jspui/handle/1010/1080

http://repositorioslatinoamericanos.uchile.cl/handle/2250/2252139

Author

GERARDO ESCOBAR VALDERRAMA

RAYMUNDO ENRIQUE TORRES OLGUIN

MISAEL FRANCISCO MARTINEZ MONTEJANO

Institutions

Conacyt (México)

Abstract

"The present invention relates to a system to implement a phase-locked loop (PLL) which is able to provide an estimation of the angular frequency, and both the positive and negative sequences of the fundamental component of a three-phase signal. These sequences are provided in fixed reference frame coordinates."

Subjects

info:eu-repo/classification/CIP/G01R25/00

info:eu-repo/classification/CIP/G06F19/00

info:eu-repo/classification/CPC/H03L7/08

info:eu-repo/classification/cti/1

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