Fixed reference frame phase-locked loop (FRF-PLL) for unbalanced line voltage conditions

dc.creatorGERARDO ESCOBAR VALDERRAMA
dc.creatorRAYMUNDO ENRIQUE TORRES OLGUIN
dc.creatorMISAEL FRANCISCO MARTINEZ MONTEJANO
dc.date2010-05
dc.date.accessioned2018-11-19T13:51:20Z
dc.date.available2018-11-19T13:51:20Z
dc.identifierhttp://ipicyt.repositorioinstitucional.mx/jspui/handle/1010/1014
dc.identifierhttp://ipicyt.repositorioinstitucional.mx/jspui/handle/1010/1080
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/2252139
dc.description"The present invention relates to a system to implement a phase-locked loop (PLL) which is able to provide an estimation of the angular frequency, and both the positive and negative sequences of the fundamental component of a three-phase signal. These sequences are provided in fixed reference frame coordinates."
dc.formatapplication/pdf
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/CIP/G01R25/00
dc.subjectinfo:eu-repo/classification/CIP/G06F19/00
dc.subjectinfo:eu-repo/classification/CPC/H03L7/08
dc.subjectinfo:eu-repo/classification/cti/1
dc.titleFixed reference frame phase-locked loop (FRF-PLL) for unbalanced line voltage conditions
dc.typeinfo:eu-repo/semantics/patent
dc.audiencegeneralPublic


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