Actas de congresos
Evaluating And Improving Thread-level Speculation In Hardware Transactional Memories
Registro en:
978-1-5090-2140-6
2016 Ieee 30th International Parallel And Distributed Processing Symposium (ipdps 2016). Ieee, p. 586 - 595, 2016.
1530-2075
WOS:000391251800061
10.1109/IPDPS.2016.84
Autor
Salamanca
Juan; Amaral
Jose Nelson; Araujo
Guido
Institución
Resumen
This paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS). As a result it provides three contributions: (a) it shows that performance issues well-known to loop parallelism (e.g. false sharing) are exacerbated in the presence of HTM, and that capacity aborts can increase when one tries to overcome them; (b) it reveals that, although modern HTM extensions can provide support for TLS, they are not powerful enough to fully implement TLS; (c) it shows that simple code transformations, such as judicious strip mining and privatization techniques, can overcome such shortcomings, delivering speed-ups for programs that contain loop-carried dependencies. Experimental results reveal that, when these code transformations are used, speed-ups of up to 30% can be achieved for some loops for which previous research had reported slowdowns. 586 595 30th IEEE International Parallel and Distributed Processing Symposium (IPDPS) MAY 23-27, 2016 Illinois Inst Technol, Chicago, IL