| dc.creator | Salamanca | |
| dc.creator | Juan; Amaral | |
| dc.creator | Jose Nelson; Araujo | |
| dc.creator | Guido | |
| dc.date | 2016 | |
| dc.date | 2017-11-13T13:22:19Z | |
| dc.date | 2017-11-13T13:22:19Z | |
| dc.date.accessioned | 2018-03-29T05:55:06Z | |
| dc.date.available | 2018-03-29T05:55:06Z | |
| dc.identifier | 978-1-5090-2140-6 | |
| dc.identifier | 2016 Ieee 30th International Parallel And Distributed Processing Symposium (ipdps 2016). Ieee, p. 586 - 595, 2016. | |
| dc.identifier | 1530-2075 | |
| dc.identifier | WOS:000391251800061 | |
| dc.identifier | 10.1109/IPDPS.2016.84 | |
| dc.identifier | http://ieeexplore.ieee.org/document/7516055/ | |
| dc.identifier | http://repositorio.unicamp.br/jspui/handle/REPOSIP/327863 | |
| dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/1364888 | |
| dc.description | This paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS). As a result it provides three contributions: (a) it shows that performance issues well-known to loop parallelism (e.g. false sharing) are exacerbated in the presence of HTM, and that capacity aborts can increase when one tries to overcome them; (b) it reveals that, although modern HTM extensions can provide support for TLS, they are not powerful enough to fully implement TLS; (c) it shows that simple code transformations, such as judicious strip mining and privatization techniques, can overcome such shortcomings, delivering speed-ups for programs that contain loop-carried dependencies. Experimental results reveal that, when these code transformations are used, speed-ups of up to 30% can be achieved for some loops for which previous research had reported slowdowns. | |
| dc.description | 586 | |
| dc.description | 595 | |
| dc.description | 30th IEEE International Parallel and Distributed Processing Symposium (IPDPS) | |
| dc.description | MAY 23-27, 2016 | |
| dc.description | Illinois Inst Technol, Chicago, IL | |
| dc.description | | |
| dc.language | English | |
| dc.publisher | IEEE | |
| dc.publisher | New York | |
| dc.relation | 2016 IEEE 30th International Parallel and Distributed Processing Symposium (IPDPS 2016) | |
| dc.rights | fechado | |
| dc.source | WOS | |
| dc.subject | Hardware Transactional Memory | |
| dc.subject | Transactional Memory | |
| dc.subject | Thread-level Speculation | |
| dc.title | Evaluating And Improving Thread-level Speculation In Hardware Transactional Memories | |
| dc.type | Actas de congresos | |
