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Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors
(2020-05-26)
The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to ...
UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level
(2020-07-31)
The main goal of this work is to perform a first-time analysis of the thermal cross-coupling in a system composed by some devices in an integration node degree composed by advanced UTBB SOI MOSFETs through numerical ...
Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors
(2020-05-26)
The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to ...
New method for self-heating estimation using only DC measurements
(Ieee, 2018-01-01)
This paper reports a new method for estimating the thermal resistance of a device using the inverse of the transistor efficiency as a function of the power applied to the transistor's channel. The advantages of this new ...
Experimental analysis and improvement of the DC method for self-heating estimation
(2019-09-01)
This paper reports an improved method for estimating the thermal resistance of a MOSFET device using the inverse of the transistor efficiency as a function of the power applied to the transistor's channel. This method was ...
New method for self-heating estimation using only DC measurements
(2018-05-03)
This paper reports a new method for estimating the thermal resistance of a device using the inverse of the transistor efficiency as a function of the power applied to the transistor's channel. The advantages of this new ...
Avaliação do MOSFET UTBB FD-SOI com SELBOX em configuração DTMOS
(Universidade Estadual Paulista (Unesp), 2020-10-30)
O objetivo principal deste trabalho é o estudo de transistores SOI (Silicon On Insulator) UTBB (Ultra-thin Body and Buried oxide) de canal tipo-n com SELBOX (SELective Buried OXide) em configuração DTMOS (Dynamic Threshold-Voltage ...
Proposal of a p-type Back-Enhanced Tunnel Field Effect Transistor
(Ieee, 2019-01-01)
In this paper we propose a new p-type Tunnel Field Effect Transistor based on the planar Back-Enhanced structure (BE-pTFET), by removing the p-type drain doping and using a back bias to obtain similar on-state behaviors ...