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Evaluating And Improving Thread-level Speculation In Hardware Transactional Memories
(IEEENew York, 2016)
Accelerating Graph Applications Using Phased Transactional Memory
(2021-01-01)
Due to their fine-grained operations and low conflict rates, graph processing algorithms expose a large amount of parallelism that has been extensively exploited by various parallelization frameworks. Transactional Memory ...
FGSCM: A Fine-Grained Approach to Transactional Lock Elision
(2017-11-08)
Speculative Lock Elision (SLE) is a technique that allows critical sections to be executed optimistically by eliding the lock operation and enabling multiple threads to execute concurrently. In case of inconsistencies, the ...
NV-PhTM: An efficient phase-based transactional system for non-volatile memory
(2020-01-01)
Non-Volatile Memory (NVM) is an emerging memory technology aimed to eliminate the gap between main memory and stable storage. Nevertheless, today’s programs will not readily benefit from NVM because crash failures may ...
Study Of Hardware Transactional Memory Characteristics And Serialization Policies On Haswell
(Elsevier Science BVAmsterdam, 2016)
Study Of Hardware Transactional Memory Characteristics And Serialization Policies On Haswell
(ELSEVIER SCIENCE BVAMSTERDAM, 2016)
SPHT: Scalable persistent hardware transactions
(2021-01-01)
With the emergence of byte-addressable Persistent Memory (PM), a number of works have recently addressed the problem of how to implement persistent transactional memory using off-the-shelf hardware transactional memory ...
SPHT: Scalable Persistent Hardware Transactions
(Usenix Assoc, 2021-01-01)
With the emergence of byte-addressable Persistent Memory (PM), a number of works have recently addressed the problem of how to implement persistent transactional memory using off-the-shelf hardware transactional memory ...
Revisiting phased transactional memory
(2017-06-14)
In recent years, Hybrid TM (HyTM) has been proposed as a transactional memory approach that leverages on the advantages of both hardware (HTM) and software (STM) execution modes. HyTM assumes that concurrent transactions ...
Improving Transactional Code Generation via Variable Annotation and Barrier Elision
(2020-05-01)
With chip manufacturers such as Intel, IBM and ARM offering native support for transactional memory in their instruction set architectures, memory transactions are on the verge of being considered a genuine application ...