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FPGA-BASED POWER METER IMPLEMENTATION FOR THREE-PHASE THREE-WIRE AND FOUR-WIRE POWER SYSTEMS, ACCORDING TO IEEE 1459-2010 STANDARD
(Ieee, 2017-01-01)
This paper proposes an electric power measurement implementation by using an FPGA (Field Programmable Gate Arrays) device, based on the power calculation theory defined by the IEEE 1459-2010 Standard. The modules synthesized ...
FPGA-based power meter implementation for three-phase three-wire and four-wire power systems, according to IEEE 1459-2010 standard
(2018-01-12)
This paper proposes an electric power measurement implementation by using an FPGA (Field Programmable Gate Arrays) device, based on the power calculation theory defined by the IEEE 1459-2010 Standard. The modules synthesized ...
FPGA-Based Implementation of an Optimization Algorithm to Maximize the Productivity of a Microbial Electrolysis Cell
(Editorial MDPI, 2021)
In this work, the design of the hardware architecture to implement an algorithm for optimizing the Hydrogen Productivity Rate (HPR) in a Microbial Electrolysis Cell (MEC) is presented. The HPR in the MEC is maximized by ...
FPGA implementation of a critical railway interlocking system
(Institute of Electrical and Electronics Engineers, 2020-02)
An interlocking is a railway system that automatically controls that changes in routes are safely managed, avoidingtrain crashes and derailments. This article presents an analysis of the state of the art technology used ...
Implementação de processador banda base ofdma para downlink lte em fpga
(Universidade Federal do Rio Grande do NorteBRUFRNPrograma de Pós-Graduação em Engenharia ElétricaAutomação e Sistemas; Engenharia de Computação; Telecomunicações, 2011-03-31)
This work treats of an implementation OFDMA baseband processor in hardware
for LTE Downlink. The LTE or Long Term Evolution consist the last stage of
development of the technology called 3G (Mobile System Third Generation) ...
Simulation and implementation on a FPGA of a channel encoder scheme for Wimax standardSimulación e implementación en FPGA de un esquema de codificación del canal sujeto al estandar de Wimax
(USFQ PRESS, departamento editorial de la Universidad San Francisco de Quito USFQ, 2011)
Design and Implementation of a Non-pipelined MD5 Hardware Architectures using a new functional description
(IEICE Transactions on Information and Systems, 2008)