masterThesis
Implementação de processador banda base ofdma para downlink lte em fpga
Fecha
2011-03-31Registro en:
SILVA, Bruno Leonardo Mendes Tavares. Implementação de processador banda base ofdma para downlink lte em fpga. 2011. 108 f. Dissertação (Mestrado em Automação e Sistemas; Engenharia de Computação; Telecomunicações) - Universidade Federal do Rio Grande do Norte, Natal, 2011.
Autor
Silva, Bruno Leonardo Mendes Tavares
Resumen
This work treats of an implementation OFDMA baseband processor in hardware
for LTE Downlink. The LTE or Long Term Evolution consist the last stage of
development of the technology called 3G (Mobile System Third Generation) which
offers an increasing in data rate and more efficiency and flexibility in transmission with
application of advanced antennas and multiple carriers techniques. This technology
applies in your physical layer the OFDMA technical (Orthogonal Frequency Division
Multiple Access) for generation of signals and mapping of physical resources in
downlink and has as base theoretical to OFDM multiple carriers technique (Orthogonal
Frequency Division Multiplexing). With recent completion of LTE specifications,
different hardware solutions have been developed, mainly, to the level symbol
processing where the implementation of OFDMA processor in base band is commonly
considered, because it is also considered a basic architecture of others important
applications. For implementation of processor, the reconfigurable hardware offered by
devices as FPGA are considered which shares not only to meet the high requirements of
flexibility and adaptability of LTE as well as offers possibility of an implementation
quick and efficient. The implementation of processor in reconfigurable hardware meets
the specifications of LTE physical layer as well as have the flexibility necessary for to
meet others standards and application which use OFDMA processor as basic
architecture for your systems. The results obtained through of simulation and
verification functional system approval the functionality and flexibility of processor
implemented