Towards a java bytecodes compiler for nios II soft-core processor

dc.contributorUniversidade Estadual Paulista (UNESP)
dc.creatorLima, Willian S.
dc.creatorLobato, Renata S.
dc.creatorManacero, Aleardo
dc.creatorSpolon, Roberta
dc.date2014-05-27T11:24:02Z
dc.date2016-10-25T18:27:38Z
dc.date2014-05-27T11:24:02Z
dc.date2016-10-25T18:27:38Z
dc.date2009-11-19
dc.date.accessioned2017-04-06T01:37:56Z
dc.date.available2017-04-06T01:37:56Z
dc.identifierProceedings - IEEE Symposium on Computers and Communications, p. 104-109.
dc.identifier1530-1346
dc.identifierhttp://hdl.handle.net/11449/71241
dc.identifierhttp://acervodigital.unesp.br/handle/11449/71241
dc.identifier10.1109/ISCC.2009.5202253
dc.identifierWOS:000277119300017
dc.identifier2-s2.0-70449513605
dc.identifierhttp://dx.doi.org/10.1109/ISCC.2009.5202253
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/892247
dc.descriptionReconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE.
dc.languageeng
dc.relationProceedings - IEEE Symposium on Computers and Communications
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.subjectBytecodes
dc.subjectControl flows
dc.subjectDependence graphs
dc.subjectInstruction set
dc.subjectJava bytecodes
dc.subjectNIOS II
dc.subjectReconfigurable architecture
dc.subjectReconfigurable computing
dc.subjectReconfigurable devices
dc.subjectResearch topics
dc.subjectSoft-core processors
dc.subjectSource codes
dc.subjectBuilding codes
dc.subjectComputer architecture
dc.subjectHigh level languages
dc.subjectProgram compilers
dc.titleTowards a java bytecodes compiler for nios II soft-core processor
dc.typeOtro


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