dc.creatorAguilar-López,Beatriz Angélica
dc.creatorJuárez-Abad,José Antonio
dc.creatorBarahona-Avalos,Jorge Luis
dc.creatorMayoral-Lagunes,Rosalino
dc.creatorLinares-Flores,Jesús
dc.creatorContreras-Ordaz,Marco Antonio
dc.date2020-12-01
dc.date.accessioned2023-09-25T15:18:48Z
dc.date.available2023-09-25T15:18:48Z
dc.identifierhttp://scielo.senescyt.gob.ec/scielo.php?script=sci_arttext&pid=S1390-860X2020000200068
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/8824963
dc.descriptionAbstract This paper presents the design of a robust Active Disturbance Rejection Controller (ADRC) for tracking the reference trajectory of the output voltage of a flying capacitor multilevel inverter. If the dynamics of each flying capacitor and of the passive elements of the filter are considered in the dynamic model of the converter, it results a high order model, which is difficult to control. PS-PWM modulation is used in this work to keep the voltages in the flying capacitors at their nominal values, and thereby generate a second-order simple dynamic model that is easier to control. The simulation and experimental results confirm that the controller is robust in the presence of disturbances, caused by either linear or nonlinear load changes. The experimental prototype of the complete system was built, and the implementation of the controller and the modulator was carried out in a FPGA; the results obtained are shown in the final part.
dc.formattext/html
dc.languagees
dc.publisherUniversidad Politécnica Salesiana
dc.relation10.17163/ings.n24.2020.07
dc.rightsinfo:eu-repo/semantics/openAccess
dc.sourceIngenius. Revista de Ciencia y Tecnología n.24 2020
dc.subjectbalanceo natural
dc.subjectcapacitores flotantes
dc.subjectcontrol robusto
dc.subjectconvertidor de potencia
dc.subjectlinealización exacta
dc.subjectrechazo activo de perturbaciones
dc.titleControl para el voltaje de salida de un inversor multinivel de capacitores flotantes
dc.typeinfo:eu-repo/semantics/article


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