| dc.contributor | Grupo de Investigación Ecitrónica | |
| dc.creator | Moreno, Juan Manuel | |
| dc.creator | Soto Vargas, Javier Evandro | |
| dc.creator | Cabestany, Joan | |
| dc.date.accessioned | 2023-05-09T19:55:57Z | |
| dc.date.accessioned | 2023-09-06T21:16:37Z | |
| dc.date.available | 2023-05-09T19:55:57Z | |
| dc.date.available | 2023-09-06T21:16:37Z | |
| dc.date.created | 2023-05-09T19:55:57Z | |
| dc.date.issued | 2013 | |
| dc.identifier | 0925-2312 | |
| dc.identifier | https://repositorio.escuelaing.edu.co/handle/001/2311 | |
| dc.identifier | https://doi.org/10.1016/j.neucom.2012.10.038 | |
| dc.identifier | https://www.sciencedirect.com/science/article/abs/pii/S0925231213004293 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/8707178 | |
| dc.description.abstract | This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in
parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other adaptive capabilities of the system are self-routing, self-placement and runtime selfconfiguration. Additionally, it is described as an example application and a software tool that has been implemented to facilitate the development of applications to test the system. | |
| dc.description.abstract | Este artículo describe un sistema de tolerancia a fallos (FTS) implementado en una nueva arquitectura de hardware autoadaptativa. Esta arquitectura se basa en una matriz de células que implementa de forma distribuida capacidades autoadaptativas. La célula incluye un multiprocesador configurable, por lo que puede tener entre uno y cuatro procesadores trabajando en paralelo, con un modo de configuración programable que permite seleccionar el tamaño de las memorias de programa y datos. Las capacidades de autoeliminación y autorreplicación de la(s) célula(s) se llevan a cabo cuando el FTS detecta un fallo en alguno de los procesadores que la(s) incluye, de forma que esta(s) célula(s) se autodescarta(n) para futuras implementaciones. Otras capacidades adaptativas del sistema son el autoenrutamiento, la autocolocación y la autoconfiguración en tiempo de ejecución. Además, se describe una aplicación de ejemplo y una herramienta de software que se ha implementado para facilitar el desarrollo de aplicaciones para probar el sistema. | |
| dc.language | eng | |
| dc.publisher | ElSevier | |
| dc.relation | 31 | |
| dc.relation | 25 | |
| dc.relation | 121 | |
| dc.relation | N/A | |
| dc.relation | Neurocomputing | |
| dc.relation | AETHER Project Home, URL: ⟨http://www.aether-ist.org⟩ | |
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| dc.relation | J. Soto, J.M. Moreno, J. Madrenas, J. Cabestany Communication infrastructure for a self-Adaptive hardware architecture, in: Proceedings of the Reconfigurable Communication-centric Systems-on-Chip workshop (ReCoSoC 08), Barcelona, Spain, July 9–11, 2008, pp. 175–180, ISBN: 978-84-691-3603-4. | |
| dc.rights | info:eu-repo/semantics/closedAccess | |
| dc.source | https://www.sciencedirect.com/science/article/abs/pii/S0925231213004293 | |
| dc.title | A self-adaptive hardware architecture with fault tolerance capabilities | |
| dc.type | Artículo de revista | |
