dc.contributorUniversidade Estadual Paulista (UNESP)
dc.creatorCanesin, C. A.
dc.creatorGoncalves, FAS
dc.date2014-05-20T13:29:02Z
dc.date2014-05-20T13:29:02Z
dc.date2005-01-01
dc.date.accessioned2017-04-05T20:12:49Z
dc.date.available2017-04-05T20:12:49Z
dc.identifier2005 IEEE 36th Power Electronic Specialists Conference (pesc), Vols 1-3. New York: IEEE, p. 513-518, 2005.
dc.identifier0275-9306
dc.identifierhttp://hdl.handle.net/11449/9747
dc.identifier10.1109/PESC.2005.1581673
dc.identifierWOS:000237036500081
dc.identifierhttp://dx.doi.org/10.1109/PESC.2005.1581673
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/857807
dc.descriptionThis paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.
dc.languageeng
dc.publisherIEEE
dc.relation2005 IEEE 36th Power Electronic Specialists Conference (pesc), Vols 1-3
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.titleA 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device
dc.typeOtro


Este ítem pertenece a la siguiente institución