dc.creatorCerdeira A.
dc.creatorAleman M.A.
dc.creatorPavanello M.A.
dc.creatorMartino J.A.
dc.creatorVancaillie L.
dc.creatorFlandre D.
dc.date2019-08-19T23:45:08Z
dc.date2023-05-03T20:35:33Z
dc.date2019-08-19T23:45:08Z
dc.date2023-05-03T20:35:33Z
dc.date2005
dc.date.accessioned2023-08-24T11:58:27Z
dc.date.available2023-08-24T11:58:27Z
dc.identifierCERDEIRA, Antonio; ALEMÁN, Miguel; PAVANELLO, Marcelo A.; MARTINO, João Antonio; VANCAILLIE, Laurent; FLANDRE, Denis. Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear Resistor. I.E.E.E. Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005.
dc.identifier0018-9383
dc.identifierhttps://hdl.handle.net/20.500.12032/89022
dc.identifier.urihttps://repositorioslatinoamericanos.uchile.cl/handle/2250/8420703
dc.descriptionIn this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications as on-resistance and nonlinear harmonic distortion, is supported by both measurements and simulations of conventional and graded-channel (GC) fully depleted silicon-on-insultor (SOI) MOSFETs. The quasi-linear current-voltage characteristics of GC transistors show a decrease of the on-resistance as the length of the low doped region in the channel is increased, as well as an improvement in the third-order harmonic distortion (HD3), when compared with conventional transistors. A method for full comparison between conventional and GC SOI MOSFETs is presented, considering HD3 evolution with on-resistance tuning under low voltage of operation. Results demonstrate the significant advantages provided by the asymmetrical long channel transistors. © 2005 IEEE.
dc.relationIEEE Transactions on Electron Devices
dc.rightsAcesso Restrito
dc.titleAdvantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor
dc.typeArtigo


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